Over the last several decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common and important semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral dimensions of the device structure. As the dimensions of the device structure are reduced laterally, it also becomes necessary to scale down the vertical dimensions of the device.
The source/drain junction is an important vertical dimension which must be scaled down as the device structure is made smaller. For a MOS device having a channel length of less than 0.8 .mu.m, for example, the source/drain junction depths must be scaled down to less than 250 nm in order to maintain adequate device performance. A decrease in junction depths, however, limits the ability to subject the junction to silicidation since, if the junction is too shallow, the entire junction can be consumed during the silicidation process.
A number of different approaches have been proposed for forming shallow junctions in silicon. In one approach, it has been proposed to perform the implantation of the source/drain dopant after the silicide layer has been formed with diffusion of the dopant through the silicide into the substrate. Another proposed solution uses selective epitaxial growth of silicon over the source/drain regions of the device being formed. These approaches add to the expense and/or manufacturing time of the devices. A more detailed description of such processes may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 154-169.